A research team from the Korea Advanced Institute of Science and Technology (KAIST) has made significant strides in semiconductor technology by developing a single-material solution that addresses a critical challenge related to charge injection in ultrathin semiconductors. This innovative approach could potentially lead to smaller and more energy-efficient artificial intelligence (AI) chips, enhancing the future of low-power electronic devices.
Universal Injector Optimizes Charge Injection
On September 16, KAIST announced that the research team, led by Professor Joonki Suh from the Department of Chemical and Biomolecular Engineering, created a ‘universal van der Waals tunneling injector’ made from tin diselenide (SnSe2). This injector efficiently provides charge to both n-type and p-type atomically thin semiconductor channels, which traditionally required separate optimizing materials for effective charge injection.
The research was conducted in collaboration with experts from several institutions, including Yonsei University, the Beijing Computational Science Research Center, the Korea Institute of Science and Technology (KIST), Hanyang University, the Ulsan National Institute of Science and Technology (UNIST), and Samsung Electronics.
Transistors act as micro switches that facilitate the flow of electric current and are found in virtually every semiconductor chip today. They can be categorized as either n-type, in which electrons are the primary charge carriers, or p-type, where ‘holes’ represent positive charge carriers. Modern semiconductor designs often utilize complementary metal-oxide-semiconductor (CMOS) technology to combine these two types, optimizing performance while minimizing energy consumption.
The advent of two-dimensional semiconductors, which can be thinner than a nanometer, provides new avenues for producing compact and efficient chips. However, efficiently injecting charge into these materials has been a challenge. Conventional methods, such as applying metal electrodes, can disrupt the atomic structure of these sensitive materials, creating energy barriers that hinder charge movement.
The KAIST team addressed these issues by using SnSe2, which relies on weak van der Waals forces for contact, preserving the integrity of the semiconductor channels. This material can adaptively offer favorable charge-injection pathways depending on whether it is paired with p-type tungsten diselenide (WSe2) or n-type molybdenum disulfide (MoS2).
Results showed that using the SnSe2 injector led to an increase in maximum drive current by over 1,000 times in p-type WSe2 transistors compared to traditional nickel electrodes. Furthermore, n-type MoS2 transistors benefited from significant improvements in switching efficiency, enabling an on/off current ratio exceeding one billion.
The team also successfully constructed a CMOS inverter, confirming its reliable operation under repeated input signals. This advancement illustrates the potential of a single material serving both n-type and p-type devices, challenging traditional manufacturing approaches.
The broader implications of this research suggest that with ongoing developments in the direct growth and large-area fabrication of two-dimensional semiconductors, future chip architectures may feature stacked layers for enhanced transistor density and energy efficiency. This advancement could prove critical in the development of next-generation AI processors and ultra-low-power electronic devices.
“This study demonstrates that efficient charge injection, one of the most challenging bottlenecks in monolayer two-dimensional semiconductors, can be addressed using a single material platform,” stated Professor Joonki Suh. The findings were published online in the international journal Advanced Materials on August 12.
Why It Matters
This achievement in semiconductor technology has the potential to transform the landscape of electronic devices, particularly in the realm of AI and low-power applications. By overcoming the challenges of efficient charge injection in ultrathin materials, the research provides a viable pathway for developing smaller, more efficient chips that can meet the growing demands of modern technology.
