AI-Driven Demand Ignites Investment in Chip Packaging Technology
TAIPEI, Nov 6 (Reuters) – A global surge in artificial intelligence is prompting significant investments in advanced chip packaging, a critical yet often overlooked aspect of semiconductor production. This shift aims to alleviate bottlenecks in the manufacturing of powerful processors as demand continues to rise.
Industry leaders, including Nvidia and AMD, alongside various firms in Taiwan, are ramping up production capacity. Equipment manufacturers are also focusing on developing new technologies to meet growing needs for AI chips, according to interviews with more than a dozen executives and analysts.
Pat Gelsinger, former CEO of Intel and now a partner at Playground Global, noted that packaging has historically been a secondary concern. “Packaging was always that thing that you just didn’t worry about,” he said. Gelsinger estimated that advanced packaging could account for nearly half the value of a chip product, as modern graphics and central processing units often integrate multiple chips.
The research firm Yole Group projects that revenue from advanced packaging will surpass traditional methods for the first time in 2026, with capital expenditures in this sector expected to approach $28 billion.
Taiwan’s TSMC, the world’s largest contract chipmaker, leads in sophisticated packaging technologies, including chip-on-wafer-on-substrate (CoWoS). This method enables the integration of separate chips, such as processors and memory, on a single base, enhancing operational speed. Companies like Nvidia, AMD, and Broadcom widely utilize this technology, particularly in AI chip development.
However, TSMC’s limited capacity has prompted some chip designers, including Nvidia, to explore alternative solutions. Nvidia is reportedly investing billions to expand CoWoS capacity at Siliconware Precision Industries (SPIL), a subsidiary of ASE Technology. This funding is aimed at increasing factory space and procuring new equipment.
A shift towards advanced packaging techniques is becoming more prevalent as manufacturers seek to combine multiple chips into single units, particularly for AI performance enhancements. Such methods allow for faster inter-chip data transfer, critical for AI operations.
The move away from TSMC has opened opportunities for smaller suppliers like Powertech Technology (PTI), which is pursuing panel-level packaging that promises to minimize waste and better accommodate larger chips. PTI’s Chairman D K Tsai remarked, “Everyone is looking for a solution outside TSMC,” indicating a growing desire among designers to diversify their sources.
PTI is collaborating with AMD and Broadcom to develop this technology, with plans to invest $400 million in an advanced packaging joint venture in Singapore. Production is anticipated to commence in 2028, according to Tsai.
As the chip industry evolves, TSMC is also developing its panel-based CoPoS technology to support larger, more complex chip packages, with pilot production expected to begin within a couple of years.
Overall, this trend reflects an industry-wide recognition of the importance of advanced packaging, particularly in the rapidly growing AI market.
